1. Field of the Invention
The present invention relates to an electrical parameter evaluation system, an electrical parameter evaluation method, and a computer-readable recording medium for recording an electrical parameter evaluation program and, more particularly, a technique for evaluating electrical parameters of MISFET with the use of the Delaunay discretization scheme, which is capable of taking the quantum-mechanical effect in account approximately by a calculation time equivalent to that required for the simulator with the use of the classical theory and also is applicable to a case impurity distribution in a semiconductor substrate is not uniform.
2. Description of the Related Art
In the prior art, in a device simulator which executes electrical parameter evaluation of MISFET represented by a silicon MOSFET numerically by virtue of numerical calculation, Boltzmann statistics based on the classical theory has been employed as the carrier distribution. However, in the silicon MOSFET, a two-dimensional quantization effect of conductive carriers as a quantum-mechanical effect cannot be disregarded because of the thinner thickness of the gate oxide film and the higher concentration in the silicon substrate according to miniaturization of the device. Therefore, difference in calculation results obtained by the classical theory and the quantum theory has been going to become significant. In other words, a high precision simulation has been going to become difficult in the device simulator using the classical theory.
As one of phenomena in which the quantum-mechanical effect appears, it has been known that, since an inversion layer capacitance calculated based on the classical theory is different from an inversion layer capacitance calculated based on the quantum theory, an effective thickness of the gate oxide film taught by calculation results calculated based on the quantum theory becomes apparently thick rather than an actual thickness of the gate oxide film. The reason for this phenomenon has been set forth in the literature, Toriumi et al., "Quantitative Investigation of Inversion Layer Capacitance", SSD85-15, IECE, 1985. In this literature, first Toriumi et al. have measured the drain current when the gate voltage is changed while applying a constant slight drain voltage and then detected a maximum value of the current amplification factor (gm). Thus, as shown in FIG. 1, a relationship between a reciprocal of the maximum value of the current amplification factor (1/gm) and the thickness of a gate oxide film (Tox) has been derived.
FIG. 1 shows experimental results of two kinds of devices which have a different substrate concentration on a device surface respectively. In both cases, an apparent thickness of the gate oxide film is increased rather than a true thickness of the gate oxide film. In other words, both the reciprocal of gm and the thickness of the gate oxide film have a linearity, but they do not pass through the origin so that the reciprocal of gm is not in proportion to the thickness of the gate oxide film. This event is inconsistent with the consideration that the reciprocal of gm should be in proportion to the thickness of the gate oxide film.
Toriumi et al. have explained the reason for this inconsistency, i.e., since conduction charges constituting the inversion layer have a limited thickness because of two-dimensional quantization as the quantum-mechanical effect, the inversion layer capacitance in the actual device becomes different from the inversion layer capacitance calculated based on the classical theory. Since such difference in the inversion layer capacitance cannot be disregarded, high precision simulation carried out by the device simulator based on the classical theory has been going to become difficult.
Under such circumstance, various technologies for electrical parameter evaluation with regard to the quantum-mechanical effect have been disclosed in the prior art.
First, as the first technology in the prior art, a simulation in which the quantum-mechanical effect in the inversion layer is taken strictly into account has been carried out by F. Stern (F. Stern, "Self-Consistent Results for n-Type Si Inversion Layers", Phys. Rev. B5, 4891 (1972)).
In this literature, Schrodinger equation and Poisson equation have been solved in a self-consistent manner along one dimensional direction perpendicular to the interface between the Si substrate and the gate oxide film in the channel region of the Si N-type MOSFET.
This method can provide the most strict solution, but it has defects such that an extremely long time is required for calculation rather than the classical theory and that two-dimensional analysis and three-dimensional analysis which are indispensable for evaluation of a short channel effect, etc. are difficult.
On the contrary, methods which can take the quantum-mechanical effect approximately into account based on physical equations in the classical theory have been considered variously.
As the second technology in the prior art, the method proposed by W. Hansch et al. will be explained for the N-type MOSFET (W. Hansch et al., "Carrier Transport near the Si/SiO.sub.2 Interface of a MOSFET", Solid-State Elec., 32, 839 (1989)). W. Hansch et al. have proposed the method in which the electron density nQM calculated quantummechanically is applied approximately to the electron density nCONV calculated based on the classical Boltzmann distribution in Eq.(1) to take the quantum-mechanical effect into account. EQU nQM=nCONV.multidot.[1-exp(-z/.lambda.)] (1)
Where z is a distance from an Si/SiO.sub.2 interface, and .lambda. is a constant which is determined by effective mass of electron, etc. Various methods similar to the Hansch et al.'s method have been proposed. However, in all such methods, the electron density nQM being calculated quantum-mechanically is approximated by use of a function of the electron density nCONV being calculated classically and a distance z from the Si/SiO.sub.2 interface. Such methods are inferior in strictness to the case where the Schrodinger equation is solved, but they can give sufficiently good approximation in practical use. In addition, a time required for calculation is small rather than the case where the Schrodinger equation is solved, and two-dimensional or three-dimensional calculation can be facilitated.
However, a thickness of the inversion layer is 6 to 8 nm whereas .lambda. in Eq.(1) is about 1 nm. Hence, there is necessity of employing a discretization mesh which has a very fine distance like 0.1 nm in the silicon substrate region which ranges from the Si/SiO.sub.2 interface to a 6 to 8 nm depth. In contrast, normally an about 2 to 4 nm distance is enough for the discretization mesh necessary for calculation of the classical theory. In brief, if the methods which are represented by W. Hansch et al. are employed, discretization mesh points which are more than twenty times those required for the calculation based on the classical theory are required, and thus a calculation time is extended correspondingly.
In addition, as the third technology in the prior art, there is a method which has been proposed by Y. Ohkura as another approximate solution (Y. Ohkura, "Quantum Effects in Si n-MOS Inversion Layer at High Substrate Concentration", Solid-State Elec., 33, 1581 (1990)). The method proposed by Y. Ohkura is that, although the solved equation in the classical theory is still used in calculation as it is, ToxMD given by Eq.(2) is employed in calculation instead of the oxide film thickness Tox in the actual device as the thickness of the gate oxide film and also VFBMD given by Eq. (3) is employed in calculation instead of VFB as the flat band voltage. The VFB can be determined by the substrate concentration of the actual device and material of the gate electrode. EQU ToxMD=Tox+.epsilon.ox.DELTA.z/.epsilon.Si (2) EQU VFBMD=VFD+qNA(.DELTA.z/2.epsilon.Si+Tox/.epsilon.ox).DELTA.z (3)
Where .epsilon. Si is a dielectric constant of silicon, .epsilon. ox is a dielectric constant of the gate oxide film, .DELTA.z is a parameter representing difference in the inversion layer capacitance between the classical theory and the quantum theory, q is an elementary charge, and NA is an acceptor concentration in the semiconductor substrate.
According to the third technology in the prior art, though the calculation is a coarse approximation, it has sufficient precision in practical use. In addition, since the discretization mesh is not needed to be formed fine in the vicinity of the Si/SiO.sub.2 interface and also the same discretization mesh as that used in the normal simulator based on the classical theory may be used, the third technology is excellent in respect of the calculation time. However, as expressed by Eq.(3), the corrected flat band voltage VFBMD is represented as a function of the impurity concentration NA in the semiconductor substrate. No problem is caused if the impurity distribution in the semiconductor substrate can be regarded as a uniform distribution. In numerous cases, since impurity introduction into the channel region by virtue of the ion implantation method is performed to define a threshold voltage after the well region has been formed in the actual device, the impurity distribution in the semiconductor substrate becomes non-uniform. For this reason, it is difficult to consider the quantum-mechanical effect for the actual device according to the Y. Ohkura's method.
Further, as the fourth technology in the prior art, there is a method which has been proposed by Tanimoto and which uses discretization performance to solve numerically the equation based on the classical theory as still another approximate solution (Tanimoto, Patent Application Publication (KOKAI) Hei 4-48744). According to this method, in the device simulator based on the classical theory with the use of a Voronoi discretization mesh, a thickness of the semiconductor (several nm) equivalent to difference in the inversion layer capacitance between the classical theory and the quantum theory is calculated, then a discretization mesh which has mesh points being closest to a semiconductor/gate insulating film interface at locations remote from the semiconductor/gate insulating film interface by the same distance as the thickness of the semiconductor equivalent to the difference in the inversion layer capacitance is set in the semiconductor, and then the quantum-mechanical inversion layer capacitance can be taken into account with the use of such discretization mesh. This method is characterized by execution of the Voronoi discretization scheme and the discretization mesh setting method, and nothing other than the above is needed.
The fourth technology in the prior art is identical in calculation time to that in the simulator based on the classical theory and is applicable to the case where the impurity distribution in the semiconductor substrate is not uniform. However, this method has defects because the Voronoi discretization mesh is employed. FIG. 2 is an example of the Delaunay discretization mesh, and FIG. 3 is an example of the Voronoi discretization mesh. In the Delaunay discretization mesh, the discretization mesh points are positioned on the interface between an external electrode and the semiconductor. While, in the Voronoi discretization mesh, the discretization mesh points are not positioned on the interface between the external electrode and the semiconductor. In the Delaunay discretization mesh, while using a discretization equation employing potential on the discretization mesh points positioned on the interface between the external electrode and the semiconductor as an unknown, simulation with regard to an external circuit as shown in FIG. 4 can be carried out. In the case of the Voronoi discretization mesh, as stated above, the discretization mesh points are not positioned on the interface between the external electrode and the semiconductor. Hence, a simulation with regard to a circuit (external circuit) other than a transistor like the circuit shown in FIG. 4 cannot be carried out. For this reason, there has existed the problem that the simulator for executing the Voronoi discretization scheme is inferior in function to the simulator for executing the Delaunay discretization scheme.